1. Field of the Invention
The present invention generally relates to computer-aided design apparatuses and computer-aided design methods, and particularly relates to a cell placement apparatus and a cell placement method.
2. Description of the Related Art
When a semiconductor integrated circuit is to be designed, power supply lines are designed first, and, then, cells are placed, followed by checking whether the consumption of electric currents by the cells satisfies predetermined requirements. To this end, the consumption of electric currents is calculated through current consumption analysis at a certain step of the designing process, and design modification is made based on the results of calculation.
As the operating frequency of semiconductor integrated circuits increases, or as the probability of cell-state transition (operating rate) increases, the consumption of currents flowing through cells and power supply lines coupled to the cells also increases. Further, as the density of cell placement increases, the number of cells receiving currents from a given power supply line increases, resulting in a large amount of current running through the power supply line. Because of this, the amount of electric current running through a given power supply line may exceed the maximum tolerable current amount of this power supply line (which is the maximum amount of electric current that can be allowed to flow through this power supply line). As a result, if the amount of electric current is extremely large, the power supply line may be severed through an electro-migration phenomenon. In order to avoid this, a check is made after cell placement in the designing of semiconductor integrated circuits as to whether the amount of electric current flowing through a power supply line is no greater than the maximum tolerable current amount. If there is a portion where a current amount exceeds a maximum tolerable current amount, the design is modified.
Such design modification is largely classified into the two following methods. In the first method, one or more cells situated at a portion where the exceeding of a maximum tolerable current amount occurs are displaced to a portion where no exceeding of a maximum tolerable current amount is detected (Patent Document 1). In the second method, the width of the power supply line is expanded, or an interconnect line in another metal layer is used as a reinforcement for the power supply line, thereby to increase the maximum tolerable current amount of the power supply line (Patent Document 2). In these two methods, a check of the exceeding of a maximum tolerable current amount and the modification of the failed portion are performed repeatedly until no failed portion is detected.
In the first method, the displacement of one or more cells may create the exceeding of a maximum tolerable current amount at another place since the probability of exceeding of a maximum tolerable current amount is high at some portions in the semiconductor integrated circuit where the operating frequency and operating rate are high. Consequently, the TAT (turnaround time) required to eliminate the exceeding of a maximum tolerable current amount increases. Further, when the density of cell placement is high, it is difficult to find a proper place to move the cells upon the exceeding of a maximum tolerable current amount, which may results in the need to perform a full-scale modification of the cell placement. This further increases the TAT.
In the second method, the routing of signal interconnect lines may be hampered since the reinforcement of the power supply line reduces availability of routing channels at some portions in the semiconductor integrated circuit where the operating frequency and operating rate are high. Moreover, depending on the amount of current consumed at a portion where the exceeding of a maximum tolerable current amount is detected, the reinforcement of the power supply line may create the exceeding of a maximum tolerable current amount at another portion (e.g., a portion closer to the source of power supply than is the point of reinforcement), which further increases the TAT required to eliminate the exceeding of a maximum tolerable current amount.
As a scheme based on another viewpoint, there is a method that determines the position of cell placement based on a ratio between power supply line resistances in two different layers (Patent Document 3). Since a checked value is a ratio of power supply line resistances (relative value) rather than a tolerable current amount (absolute value), the first method or the second method still needs to be utilized to modify the portions where the exceeding of a maximum tolerable current amount is detected, despite the fact that the shortening of the TAT is achievable to some extent by restricting the initial placement of cells to reduce the number of the portions where the exceeding of a maximum tolerable current amount occurs.
[Patent Document 1] Japanese Patent Application Publication No. 11-87518
[Patent Document 2] Japanese Patent Application Publication No. 04-287945
[Patent Document 3] Japanese Patent Application Publication No. 07-106533
Accordingly, there is a need for a cell placement scheme that achieves cell placement without increasing the TAT and without the exceeding of a maximum tolerable current amount.